1. Field of the Invention
The invention relates to power management, and more particularly to a power saving method for a computer system.
2. Description of the Related Art
FIG. 1 is a schematic view of a computer system.
The computer system 100 comprises a processor 110 and a chipset 130. Chipset 130 further comprises an interrupt controller 131 and a SMC 133, coupled to processor 110 via a lightning data transport (LDT) bus. When an operating system of computer 100 operates, an LDT_STOP pin is deasserted (connection, LDTSTOP#=HIGH) using SMC 133 to enable the LDT bus, thereby enabling data transmission between processor 110 and chipset 130. When the operating system enters a power saving mode, processor 110 issues a halt instruction to enter the C1 state (a power saving state) from the C0 state (an operational state).
Next, processor 110 broadcasts a sleep message to other components (such as chipset 130, device 150, and others) to reduce system resource consumption, by, for example, lowering operational frequency, voltage, and the like, while the LDT_STOP pin is still deasserted (connection, LDTSTOP#=HIGH) such that the LDT bus is still enabled. If device 150 sends an interrupt request (IRQ) to chipset 130, interrupt controller 131 receives and transmits the IRQ to processor 110. When receiving the IRQ, processor 110 is waked up from the C1 state (a power saving state) to the C0 state (an operational state) while the LDT_STOP pin is still deasserted (connection, LDTSTOP#=HIGH) that the LDT bus is still enabled.
As described, the LDT_STOP pin is always deasserted (connection, LDTSTOP#=HIGH) even if computer system 100 and processor 110 enter a power saving mode (C1 state), wasting system resources or power. Thus, an improved power saving method and apparatus is desirable.